VLSI TECHNOLOGY Introduction to VLSI

• What is VLSI
• VLSI Design Flow
• ASIC
• Soc

Fundamentals of Digital Design

• Basis Digital Circuits
• Logic gates Boolen Algebra
• Number Systems
• Digital Logic Families

Combinational Logic Desig

• Multiplexers
• MUX based design for digital circuits
• Demultiplexers/Decoders
• Adders/Sub tractors
• BCD Arithmetic ALU
• Comperators Parity Generator
• Code Converters/Encoders
• Decoders
• Multiplers/Divider

Sequential Logic Design Principles

• Bistable Elements.
• Latches and Flip-Flops
• Counters and its application
• Synchronous Design methodology
• Impediments to Synchronous Design
• Shift Registers
• Design Examples Case studies

Advanced Digital Design

• Synchronous/Asynchronous Sequential Circuits.
• Clocked Synchronous State-Machine Analysis.
• Clocked Synchronous State-Machine Design
• Finite State Machine
• Mealy and Moore machines
• State reduction technique
• Sequence Detectors
• ASM Charts
• Synchronizer Failure and Metastability Estimation
• Clock Dividers
• Synchronizers Arbiters
• FIFO Pipelining
• PLD + CPLD

VHDL OVERVIEW AND CONCEPTS

• Types, object
• classes, design units, compilation elaboration.

BASIC LANGUAGE ELEMENTS

• Lexical elements,
• syntax, operators, types and subtypes (scalar, physical,
• real, composite (arrays, records),access files).

CONTROL STRUCTURES: Control Structures and rules

• DRIVERS: Resolution function, drivers (definition,
• initialization, creation), ports
• TIMING: Signal attributes. "wait" statement, delta time,
• simulation engine, modeling with delta time delays, VITAL
• tables, inertial / transport delay

ELEMENTS OF ENTITY/ARCHITECTURE

• architecture, (process, concurrent signal assignment,
• component instantiation and port association rules,
• concurrent procedure, generate, concurrent assertion,
• block, guarded signal).
• SUBPROGRAMS: Rules and guidelines (unconstrained
• arrays. interface class, initialization, implicit signal
• attributes, drivers, signal characteristics in procedure
• calls, sides effects),overloading, functions (resolution
• function, operator overloading, function(resolution
• function, operator overloading), concurrent procedure.
• Declaration., body, deferred Constant,
• "use" Clause, Signals, resolution function, subprograms,
• converting typed objects to strings, TEXTIO, printing
• objects, linear feedback shift register, random number
• generation compilation order

USER DEFINED ATTRIBUTES, SPECIFICATIONS, AND CONFIGURATIONS

• specifications, configuration specification and binding,.
• configuration declaration and binding, configuration of
• generate statements.

DESIGN FOR SYNTHESIS

• Constructs, register
• inference, combinational logic inference. state machine
• and design styles, arthimetic operations.

FUNCTION MODELS AND TESTBENCHES

• Test bench design methodology, BFM Modeling, Scenario generation
• schemes, waveform generator, client/server, text
• command file, binary command file.

VITAL

• Overview, features, model, pin-to-pin delay
• modeling style, distributed delay modeling style.
• Datatype

Overview of Digital Design with Verilog HDL

• Evolution of CAD, emergence of HDLs, typical HDLbased
• design flow, why Verilog HDL?, trends in HDLs.

Hierarchical Modeling Concepts

• Top-down and bottom-up design methodology,
• differences between modules and module instances,
• parts of a simulation, design block, stimulus block.

Basic Concepts

• Lexical conventions, data types, system tasks, compiler
• directives.

Modules and Ports

• Module definition, port declaration, connecting ports,
• hierarchical name referencing.

Gate-Level Modeling

• Modeling using basic Verilog gate primitives, description
• of and/or and buf/not type gates, rise, fall and turn-off
• delays, min, max, and typical delays.

Dataflow Modeling

• Continuous assignments, delay specification,expressions,
• operators, operands, operator types.

Behaviour Modeling

• Structured procedures, initial and always, blocking and
• nonblocking statements, delay control, generate
• statement, event control, conditional statements,
• multiway branching, loops, sequential and parallel blocks.

Tasks and Functions

• Differences between tasks and functions, declaration,
• invocation, automatic tasks and functions,
• Datatype

Tasks and Functions

• invocation, automatic tasks and functions,
• system tasks.

List of projects

• Microcontroller Design,
• RISC CISC Processor Design,
• Multiplier / Divider using different Algorithms,
• DDR Controller,
• JTAG: Boundary SCAN,
• JPC, PCI, Ethernet,
• I2C,AMBA, Wishbone Conmax,
• CORDIC Algorithm