VLSI VERILOG Training

Introduction to VLSI

• What is VLSI
• VLSI Design Flow
• ASIC
• SOC

SECTION A:Fundamentals of Digital Design

• FUNDAMENTALS
• Combinational Logic Design
• Sequential Logic Design Priciples

SECTION B: Advanced Digital Design

• Synchronous/Asynchronous Sequential Circuits
• ASM charts
• Finite state machine
• Mealy and Moore machine
• State reduction technique
• Sequence Detectors
• Clock Dividers
• Synchronizers Arbiters
• FIFO & Pipelining

MINOR PROJECT

• Lab Sessions on ModelSIM

SECTION C: VERILOG

• Overview of Digital Design with Verilog HDL
• Hierarchical Modeling Concepts
• Basic Concepts
• Basic Concepts
• Gate-Level Modeling
• Dataflow Modeling
• Behavioral Modeling
• Tasks and Functions
• Useful Modeling Techniques

Advanced Verilog Topics

• Timing and Delays
• Switch-Level Modeling
• User-Deined Primitives
• Logic Synthesis with Verilog HDL
• Advanced Verification Techniques